module ysyx_23060189_UART #
(
  parameter integer dataWidth = 32,
  parameter integer addrWidth = 32
)
(
  /* Slave <=> Slave interface */
  input  wire                 ACLK,
  input  wire                 ARESETn,

  input  wire                 ren,
  input  wire [addrWidth-1:0] raddr,
  output wire [dataWidth-1:0] rdata,
  output wire                 rvalid,

  input  wire                 wen,
  input  wire [addrWidth-1:0] waddr,
  input  wire [dataWidth-1:0] wdata,
  input  wire [7:0]           wmask,
  output reg                  wdone
);
  // reg define
  reg [7:0] device_register;
  reg status_register;

  // not read
  assign rdata  = 0;
  assign rvalid = 1'b0;

  // device register
  always @(posedge ACLK) begin
    if (ARESETn == 0) device_register <= 0;
    else if (wen) device_register <= wdata[7:0];
    else device_register <= device_register;
  end

  // status register
  always @(posedge ACLK) begin
    if (ARESETn == 0) status_register <= 0;
    else status_register <= wen;
  end

  // output data
  always @(posedge ACLK) begin
    if (ARESETn == 0) wdone <= 1'b0;
    else if (status_register) begin
      $write("%c", device_register);
      wdone <= 1'b1;
    end
    else wdone <= 1'b0;
  end
 
endmodule
